2,211 research outputs found

    A model for evaluating the institutional costs and benefits of ICT initiatives in teaching and learning in higher education

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    Significant investments are being made in the application of new information and communications technologies (ICT) to teaching and learning in higher education. However, until recently, there has been little progress in devising an integrated cost‐benefit model that decision‐makers can use to appraise ICT investment options from the wider institutional perspective. This paper describes and illustrates a model that has been developed to enable evaluations of the costs and benefits of the use of ICT. The strengths and limitations of the model are highlighted and discussed

    The importance of cost‐benefit analysis: A response

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    The critique by Draper raises some interesting points that we did not have space to discuss in our published paper. As he points out, taking a purely quantitative approach to the evaluation of ICT investments in teaching and learning is wholly inappropriate. However, in this transitional period, where ICT applications are new and the effects on operational processes within higher education institutions are unknown, it is not only qualitative issues that need to be investigated but also the potential changes to the scope and nature of the costs incurred by institutions. While the small-scale, and localized, introduction of ICT in teaching might only affect the time and effort of a few individual academics, large-scale deployment of the same methodology may require substantial institutional investment (for example, in network infrastructure, hardware, licenses, support staff). The CBA model encourages institutions to consider and record all the cost implications of their strategies, not in an attempt to quantify the outputs (benefits) of these new learning processes but to identify and quantify the inputs to these processes. These quantitative inputs can then be evaluated in the context of qualitative outputs

    Optimistic barrier synchronization

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    Barrier synchronization is fundamental operation in parallel computation. In many contexts, at the point a processor enters a barrier it knows that it has already processed all the work required of it prior to synchronization. The alternative case, when a processor cannot enter a barrier with the assurance that it has already performed all the necessary pre-synchronization computation, is treated. The problem arises when the number of pre-sychronization messages to be received by a processor is unkown, for example, in a parallel discrete simulation or any other computation that is largely driven by an unpredictable exchange of messages. We describe an optimistic O(log sup 2 P) barrier algorithm for such problems, study its performance on a large-scale parallel system, and consider extensions to general associative reductions as well as associative parallel prefix computations

    Using classroom communication systems to support interaction and discussion in large class settings

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    Teaching methods that promote interaction and discussion are known to benefit learning. However, large class sizes make it difficult to implement these methods. Research from the United States has shown that an electronic classroom communication system (CCS) can be used to support active discussion in large lecture classes. This investigation extends that research and it evaluates students’ and teachers’ experiences of CCS technology in the context of two different modes of discussion — peer‐group and class‐wide discussion. With CCS technology, students’ answers to multiple‐choice concept tests are collated in real time with the class results fed back as a histogram. This information serves as the trigger for each mode of discussion. This paper explores the unique contribution of CCS technology, the relative strengths of peer‐ and class‐wide discussion and some practical implementation issues

    Conservative parallel simulation of priority class queueing networks

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    A conservative synchronization protocol is described for the parallel simulation of queueing networks having C job priority classes, where a job's class is fixed. This problem has long vexed designers of conservative synchronization protocols because of its seemingly poor ability to compute lookahead: the time of the next departure. For, a job in service having low priority can be preempted at any time by an arrival having higher priority and an arbitrarily small service time. The solution is to skew the event generation activity so that the events for higher priority jobs are generated farther ahead in simulated time than lower priority jobs. Thus, when a lower priority job enters service for the first time, all the higher priority jobs that may preempt it are already known and the job's departure time can be exactly predicted. Finally, the protocol was analyzed and it was demonstrated that good performance can be expected on the simulation of large queueing networks

    Rectilinear partitioning of irregular data parallel computations

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    New mapping algorithms for domain oriented data-parallel computations, where the workload is distributed irregularly throughout the domain, but exhibits localized communication patterns are described. Researchers consider the problem of partitioning the domain for parallel processing in such a way that the workload on the most heavily loaded processor is minimized, subject to the constraint that the partition be perfectly rectilinear. Rectilinear partitions are useful on architectures that have a fast local mesh network. Discussed here is an improved algorithm for finding the optimal partitioning in one dimension, new algorithms for partitioning in two dimensions, and optimal partitioning in three dimensions. The application of these algorithms to real problems are discussed

    Inflated speedups in parallel simulations via malloc()

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    Discrete-event simulation programs make heavy use of dynamic memory allocation in order to support simulation's very dynamic space requirements. When programming in C one is likely to use the malloc() routine. However, a parallel simulation which uses the standard Unix System V malloc() implementation may achieve an overly optimistic speedup, possibly superlinear. An alternate implementation provided on some (but not all systems) can avoid the speedup anomaly, but at the price of significantly reduced available free space. This is especially severe on most parallel architectures, which tend not to support virtual memory. It is shown how a simply implemented user-constructed interface to malloc() can both avoid artificially inflated speedups, and make efficient use of the dynamic memory space. The interface simply catches blocks on the basis of their size. The problem is demonstrated empirically, and the effectiveness of the solution is shown both empirically and analytically

    The cost of conservative synchronization in parallel discrete event simulations

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    The performance of a synchronous conservative parallel discrete-event simulation protocol is analyzed. The class of simulation models considered is oriented around a physical domain and possesses a limited ability to predict future behavior. A stochastic model is used to show that as the volume of simulation activity in the model increases relative to a fixed architecture, the complexity of the average per-event overhead due to synchronization, event list manipulation, lookahead calculations, and processor idle time approach the complexity of the average per-event overhead of a serial simulation. The method is therefore within a constant factor of optimal. The analysis demonstrates that on large problems--those for which parallel processing is ideally suited--there is often enough parallel workload so that processors are not usually idle. The viability of the method is also demonstrated empirically, showing how good performance is achieved on large problems using a thirty-two node Intel iPSC/2 distributed memory multiprocessor
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